A typical electrically erasable and programmable non-volatile memory cell (EEPROM) retains binary data by storing an amount of electrical charge on a floating gate structure in MOS transistors. By convention, a charged floating gate represents the logic “1” state (erased state) while an uncharged floating gate represents the logic “0” state (programmed state). To infuse the floating gate of a MOS transistor with electrons (i.e. to erase), a high voltage Vpp is applied to its gate while its source is connected to ground. A charged floating gate increases the threshold voltage of the transistor. To discharge the floating gate device (i.e. to program), Vpp is applied to its drain and its gate is connected to ground.
FIG. 1 shows how floating gate transistors 10 are typically connected in an EEPROM memory array 22. Each floating gate transistor 10 is paired up with an access transistor 12, forming a memory cell, in which the source of the access transistor 12 is connected to the drain of the floating gate transistor 10. The drain of the access transistor 12 taps into a bit line 16 that is common to the drains of all of the access transistors 12 in the same column. The source of the floating gate transistor 10 is connected to ground. A data column latch 24 is connected to one end of the bit line 16 and a bit line select transistor 28 is connected to the other end. The gate of the access transistor 12 is connected to a word line 20 that is common to the gates of all of the access transistors 12 in the same row. The floating gate transistors 10 in each row are typically subdivided into word or byte size groups and the gates of the floating gate transistors 10 in each group are connected to the source of a word select transistor 14. The drain of the word select transistor 14 connects to a Vref line 18 that provides a stable reference voltage to the memory cell during read or connects to Vpp during erase. One end of the Vref line 18 is connected to a Vref column latch 26 and the other end is connected to a reference voltage block 40 through a transistor 30 that is controlled by an address decoder 42. The gate of the word select transistor 14 is connected to the word line 20.
The programming of memory cell proceeds in three stages: load, erase and write. In the load stage, a Y address decoder 44 receives a coded address and sends a decoded address 42 to the bit line selection block 32, turning on selected bit line select transistors 28, which provides a direct connection between the selected column latches 25 and selected data input terminal 38. The connection allows the signals in the data input terminal 38 to be applied to selected bit lines 16. With an assertive signal applied at the load terminal 46 of column latches 24, the data signals from the data input terminal 38 is latched onto the column latches 24.
In the erasure stage, electrons are injected into the floating gate structure by holding the gates of floating gate transistor 10 at an elevated voltage Vpp, while at the same time grounding its drain. The Vpp is provided from elevated voltage (Vpp) terminal 48 by the Vref column latch 26 through the word select transistor 14. Both of the word select transistor 14 and the access transistor 12 are turned on by an X address decoder 50 through the word line 20. Once the content in selected memory cells are erased, it is ready to be written.
During the write stage, the X address decoder 50 continues to apply a high voltage Vpp to the gates of word select transistors 14 and the access transistors 12. At the same time, the bit line column latch 24 applies a high voltage Vpp or high impedance to the selected bit lines 16 depends on whether the stored data is a logic “0” or a logic “1”. When a Vpp is exerted on the bit line 16, electron charges are extracted from the floating gate structure of the selected floating gate transistors 10, thereby programming the transistor 10 for the storage of a logic “0”. When a high impedance present on the bit line 16, nothing will happen to the floating gate transistor 14, which will retain its erase state of logic “1”.
In a read operation, the X address decoder 50 and Y address decoder 44 specify the location of memory. The memory contents in the specified memory are then presented onto the bit line 16. A sense amplifier 36 connected at one end of the bit line detects the data signal and sends them out to an output terminal 37.
From the above description, it should be clear that both the loading and the reading operation require the service of the Y address decoder 44, the bit line 16, the bit line select circuit 32 and therefore, the two steps cannot be performed simultaneously. However, it would be desirable to have a system wherein the reading and loading operation can be performed simultaneously, thereby speeding up the memory access processes.